FPGA or ASIC Verification Designer - KEY

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Job Description

This job might be for you if:

You want your contributions to make a noticeable impact. You love taking on difficult challenges and the satisfaction that comes from finding creative solutions. If you don’t know the answer, you’ll dig until you find it. You play nice with humans and machines. You think on your feet. You like learning new things, and you can learn quickly. You can explain just about anything to anyone. You’re going to take ownership of the time you spend with us and truly make a difference.

A typical day might include:

– Read up on a new standard to understand the system’s desired behavior

– Create a new UVM component in SystemVerilog to model the behavior of a packet source

– Connect the component in the testbench and write a new testcase to cover a feature

– Update the testbench design spec

– Update the verification plan with the testcase result

– Work with project management to track progress

– Run a regression and check the system functional coverage

– Work with the RTL designer to debug a failing testcase

– Improve a script for automatic register generation

– Push the changes in GIT and tag a new release

– Work with software and RTL designers in the lab to get a device running

– Run some tests to characterize the maximum DMA bandwidth

– Update Redmine with the progress made on current tasks

Job Qualifications

You have:

– Knowledge of SystemVerilog and UVM

– Expertise in SoC FPGA interconnects such as Avalon or AXI4 interfaces

– Experience with Modelsim, VCS, Altera Quartus or Xilinx Vivado Tools

– Familiarity with FPGA workflows including RTL design and synthesis

– Expertise in RTL debugging through waveform simulations and self-checking testbenches

– Familiarity with hardware integration and lab tools

You might also have:

– Knowledge of VMM, OVM, Specman or VERA

– Experience with ARM multi-processor systems within an embedded Linux environment

– Knowledge of PCI Express, Ethernet, 10GE, and other protocols


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